Please use this identifier to cite or link to this item:
https://hdl.handle.net/10316/102728
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Falcao, Gabriel | - |
dc.contributor.author | Gomes, Marco | - |
dc.contributor.author | Silva, Vítor | - |
dc.contributor.author | Sousa, Leonel | - |
dc.contributor.author | Cacheira, João | - |
dc.date.accessioned | 2022-10-10T10:17:42Z | - |
dc.date.available | 2022-10-10T10:17:42Z | - |
dc.date.issued | 2012 | - |
dc.identifier.issn | 1687-1499 | - |
dc.identifier.uri | https://hdl.handle.net/10316/102728 | - |
dc.description.abstract | Semi-parallel architectures for decoding Digital Video Broadcasting-Satellite 2 (DVB-S2) Low-Density Parity-Check (LDPC) codes have improved Very Large Scale Integration (VLSI) solutions, but their design is challenging from several perspectives. In order to conveniently exploit parallelism for obtaining VLSI LDPC decoders that occupy small circuit areas and demand low power consumption, we propose in this article a novel ASIC reconfigurable approach that exploits efficiently the memory block reshaping required to use a reduced number of processor nodes. We exploit different memory tiling configurations to reduce the memory area about 20%. The proposed architecture was synthesized for a 90 nm process design with a variable number of processor nodes and a competitive circuit area of 6.2 mm2 was achieved. The operating frequency simultaneously guarantees throughputs superior to 90 Mbps, as required by DVB-S2, and low levels of power consumption | pt |
dc.language.iso | eng | pt |
dc.relation | FCT - SFRH/BD/37495/2007 | pt |
dc.relation | FCT - SFRH/BD/38338/2007 | pt |
dc.relation | FCT - project PEst-OE/EEI/LA0008/2011 | pt |
dc.rights | openAccess | pt |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | pt |
dc.subject | LDPC decoding | pt |
dc.subject | DVB-S2 | pt |
dc.subject | VLSI | pt |
dc.subject | ASIC | pt |
dc.subject | memory tiling | pt |
dc.subject | semi-parallel architecture | pt |
dc.subject | M-factorizable architecture | pt |
dc.subject | Low-power consumption | pt |
dc.subject | high-throughput | pt |
dc.title | Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design | pt |
dc.type | article | pt |
degois.publication.firstPage | 98 | pt |
degois.publication.issue | 1 | pt |
degois.publication.title | Eurasip Journal on Wireless Communications and Networking | pt |
dc.peerreviewed | yes | pt |
dc.identifier.doi | 10.1186/1687-1499-2012-98 | - |
degois.publication.volume | 2012 | pt |
dc.date.embargo | 2012-01-01 | * |
uc.date.periodoEmbargo | 0 | pt |
item.grantfulltext | open | - |
item.cerifentitytype | Publications | - |
item.languageiso639-1 | en | - |
item.openairetype | article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.fulltext | Com Texto completo | - |
crisitem.author.researchunit | IT - Institute of Telecommunications | - |
crisitem.author.researchunit | IT - Institute of Telecommunications | - |
crisitem.author.orcid | 0000-0003-1124-525X | - |
crisitem.author.orcid | 0000-0003-2439-1184 | - |
Appears in Collections: | I&D IT - Artigos em Revistas Internacionais FCTUC Eng.Electrotécnica - Artigos em Revistas Internacionais |
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Configurable-Mfactor-VLSI-DVBS2-LDPC-decoder-architecture-with-optimized-memory-tiling-designEurasip-Journal-on-Wireless-Communications-and-Networking.pdf | 760.79 kB | Adobe PDF | View/Open |
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